The present invention relates to a semiconductor memory and, more particularly, to a technique which may effectively be applied to, for example, a static type RAM (Random-Access Memory) that is accessed with data consisting of a plurality of bits.
A variety of semiconductor memories such as a static RAM that is accessed with data consisting of a plurality of bits, e.g., in units of bytes, are described, for example, in "Hitachi IC Memory Data Book", Hitachi Ltd., September 1983, pp. 226 to 232.
Conventional semiconductor memories of the type described above have relatively small storage capacities which are prepared in the form of individual memory integrated circuits and incorporate no error detecting circuits such as ones adapted for performing parity check.
A memory system which requires a relatively large storage capacity is realized by combining together a plurality of semiconductor memories. In the case where a memory system needs to have an error detecting function such as a parity check function, it is conventional practice to provide a predetermined parity check circuit in the memory system or execute processing of a program for parity check in a processing unit.